preliminary
0.18 m six layer metal cmos process 1.8/2.5/3.3 v drive capable i/o 960 logic cells 248,160 max system gates up to 250 i/o pins twenty 2,304-bit dual port high performance sram blocks 46,100 ram bits ram/rom/fifo wiza rd for automatic configuration configurable and cascadable ! high performance enhanced i/o (eio)? less than 3 ns tco programmable slew rate control programmable i/o standards: lvttl, lvcmos, pci, gtl+, sstl2, and sstl3 eight independent i/o banks three register configurations: input, output, and output enable "# $% &$ nine global clock networks: one dedicated eight programmable 20 quad-net networks?five per quadrant 16 i/o controls?two per i/o bank four phase locked loops #' " ("
10 ecus provide integrat ed multiply, add, and accumulate functions.
embedded ram blocks pll pll fabric 10 embeded computational units embedded ram blocks pll pll ) #"" *"+ "
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3 *(at v cc = 2.5 v, ta = 25 c, worst case corner, speed grade = -7 (k = 1.16)) the ac specifications are provided from 4 to 4 1 . logic cell diagrams and waveforms are provided from / to 0 .
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" t pd combinatorial delay of the longest path: time taken by the combinatorial circuit to output - 0.257 ns t su setup time: time the synchronous input of the flip-flop must be stable before the active clock edge 0.22 ns - t hl hold time: time the synchronous input of the flip-flop must be stable after the active clock edge 0 ns - t co clock-to-out delay: the amount of time taken by the flip-flop to output after the active clock edge. - 0.255 ns t cwhi clock high time: required minimum time the clock stays high 0.46 ns - t cwlo clock low time: required minimum time that the clock stays low 0.46 ns - t set set delay: time between when the flip-flop is ?set? (high) and when the output is consequently ?set? (high) - 0.18 ns
preliminary 6 !"#$% t reset reset delay: time between when the flip-flop is ?reset? (low) and when the output is consequently ?reset? (low) - 0.09 ns t sw set width: time that the set signal remains high/low 0.3 ns - t rw reset width: time that the reset signal remains high/low 0.3 ns -
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" set d clk reset q set reset q clk t cwhi (min) t cwlo (min) t reset t rw t set t sw
preliminary 7 !& '#$% ( ) &""
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# $*" ) logic cells (internal) clock signal generated internally 1.51 ns (max) clock pad clock signal generated externally 2.06 ns (max) 1.73 ns (max) clk d q t su t hl t co quad net
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global clock pin delay to quad net - 1.34 ns t bgck global clock tree delay (quad net to flip-flop) - 0.56 ns
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, 5 " t swa wa setup time to wclk: time the write address must be stable before the active edge of the write clock 0.675 ns - t hwa wa hold time to wclk: time the write address must be stable after the active edge of the write clock 0 ns - t swd wd setup time to wclk: time the write data must be stable before the active edge of the write clock 0.654 ns - programmable clock external clock global clock buffer global clock t pgck t bgck clock select wa wd we wclk re rclk ra rd ram module [9:0] [17:0] [9:0] [17:0] asyncrd
preliminary . 0 -./ &1 + #" t hwd wd hold time to wclk: time the write data must be stable after the active edge of the write clock 0 ns - t swe we setup time to wclk: time the write enable must be stable before the active edge of the write clock 0.623 ns - t hwe we hold time to wclk: time the write enable must be stable after the active edge of the write clock 0 ns - t wcrd wclk to rd (wa = ra): time between the active write clock edge and the time when the data is available at rd - 4.38 ns
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4" 5 " t sra ra setup time to rclk: time the read address must be stable before the active edge of the read clock 0.686 ns - t hra ra hold time to rclk: time the read address must be stable after the active edge of the read clock 0 ns - t sre re setup time to wclk: time the read enable must be stable before the active edge of the read clock 0.243 ns - t hre re hold time to wclk: time the read enable must be stable after the active edge of the read clock 0 ns -
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, 5 " t swa t swd t swe t hwa t hwd t hwe t wcrd old data new data wclk wa wd we rd
preliminary 8 -./ &1 + 2.1 + -' t rcrd rclk to rd: time between the active read clock edge and the time when the data is available at rd - 4.38 ns #
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4" r pdrd ra to rd: time between when the read address is input and when the data is output - 2.06 ns
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4" 5 " t sra t hra rclk ra t sre t hre t rcrd old data new data re rd r pdrd
preliminary 9 345
3 "-" e r q d r q e r q d + - pad output enable register output register input register d pad t isu t sid + - q e d r
preliminary :
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# !" , 5 " t isu input register setup time: time the synchronous input of the flip-flop must be stable before the active clock edge 2.50 ns - t ihl input register hold time: time the synchronous input of the flip-flop must be stable after the active clock edge 0 ns - t ico input register clock-to-out: time taken by the flip-flop to output after the active clock edge - 1.08 ns t irst input register reset delay: time between when the flip-flop is ?reset? (low) and when the output is consequently ?reset? (low) - 0.99 ns t iesu input register clock enable setup time: time ?enable? must be stable before the active clock edge 0.37 ns - t ieh input register clock enable hold time: time ?enable? must be stable after the active clock edge 0 ns -
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, ( " t sid (lvttl) lvttl input delay: low voltage ttl for 3.3 v applications - 0.34 ns t sid (lvcmos2) lvcmos2 input delay: low voltage cmos for 2.5 v and lower applications - 0.42 ns t sid (lvcmos18) lvcmos18 input delay: low voltage cmos for 1.8 v applications - - t sid (gtl+) gtl+ input delay: gunning transceiver logic - 0.68 ns t sid (sstl3) sstl3 input delay: stub series terminated logic for 3.3 v - 0.55 ns t sid (sstl2) sstl2 input delay: stub series terminated logic for 2.5 v - 0.61 ns
preliminary 1 3 "-" 5""-" r clk d q isu ihl ico iesu ieh irst e t t t t t t pad output register
preliminary 5""-"
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# !" , " t outlh output delay low to high (90% of h) - 0.40 ns t outhl output delay high to low (10% of l) - 0.55 ns t pzh output delay tri-state to high (90% of h) - 2.94 ns t pzl output delay tri-state to low (10% of l) - 2.34 ns t phz output delay high to tri-state - 3.07 ns t plz output delay low to tri-state - 2.53 ns t cop clock-to-out delay (does not include clock tree delays) - 3.15 ns (fast slew) 10.2 ns (slow slew)
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& & & rising edge 1.7 v/ns 0.6 v/ns falling edge 1.9 v/ns 0.6 v/ns l h l h t outlh t outhl l h z t pzh l h z t pzl l h z t plz l h z t phz
preliminary /
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& & & rising edge - v/ns - v/ns falling edge - v/ns - v/ns
preliminary 6 ##
the dc specifications are provided in 4 / through 4 7 .
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5 5 v cc voltage -0.5 v to 3.6 v dc input current 20 ma v ccio voltage -0.5 v to 4.6 v esd pad protection 2000 v inref voltage 2.7 v leaded package storage temperature -65 c to + 150 c input voltage -0.5 v to v ccio +0.5 v laminate package (bga) storage temperature -55 c to + 125 c latch-up immunity 100 ma
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# (" " " " v cc supply voltage 2.3 2.7 2.3 2.7 2.3 2.7 v v ccio i/o input tolerance voltage 1.62 3.6 1.62 3.6 1.62 3.6 v ta ambient temperature -55 -40 85 0 70 c tc case temperature - 125 - - - - c k delay factor -6 speed grade 0.42 1.35 0.43 1.26 0.46 1.23 n/a -7 speed grade 0.42 1.28 0.43 1.19 0.46 1.16 n/a
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i i i or i/o input leakage current v i = v ccio or gnd -10 10 a i oz 3-state output leakage current v i = v ccio or gnd -10 10 a c i input capacitance a
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preliminary 7 #' " (" <#(= traditional programmable logic ar chitectures do not implement arithmetic functions efficiently or effectively?these functions require high logic cell usage while garnering only moderate performance results. the ql6250-e architecture allows for functionality above and be yond that achievable using programmable logic devices. by embedding a dyna mically reconfigurable computational unit, the ql6250-e device can address various arithmetic fu nctions efficiently. th is approach offers greater performance than tradit ional programmable logic implementations. the embedded block is implemented at the transistor level as shown in . . 6 the 10 ql6250-e ecu blocks are placed next to the sram circuitry for efficient memory/instruction fetch and addressing for dsp algorithmic implementations. ten 8-bit multiply-accumulate (m ac) functions can be implemente d per cycle for a total of 1 billion macs/s when clocked at 100 mhz. addition al mac functions can be implemented in the programmable logic. the modes for the ecu block are dynamically re -programmable through the programmable logic as shown in 4 0 . a[0:15] b[0:15] sign2 sign1 cin s1 s2 s3 a b c d 3-4 decoder 8-bit multiplier 17 inc. cout 16-bit adder 17-bit register 2-1 mux 2-1 mux 3-1 mux q[0:16] clk reset dq 00 01 10 a[0:7] a[8:15]
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preliminary .
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= instead of requiring extra components, designer s simply need to instantiate one of the pre- configured models described in this section and listed in 4 . . the quicklogic built-in plls support a wider range of frequencies than many other plls. also, quic klogic plls can be cascaded to support different rang es of frequency multiplications or divisions, driving the device at a faster or slower rate than the incoming cl ock frequency. most impo rtantly, they achieve a very short clock-to-out ti me?generally less than 3 ns. this lo w clock-to-out time is achieved by the pll subtracting the clock tree delay through the feedback path , effectively making the clock tree delay zero. 8 illustrates a typical quicklogic fpga pll. * 7 f in represents a very stable high-frequency input cl ock and produces an accu rate signal reference. this signal can either bypass the pll entirely, thus entering the clock tree di rectly, or it can pass through the pll itself. within the pll, a voltage-controlled oscillator (vco) is added to the circuit. the external f in signal and the local vco form a control loop. the vco is multiplied or divided down to the reference frequency, so that a phase dete ctor (the crossed circle in 8 ) can compare the two signals. if the phases of the external and local signals are not within the tolerance required, the phase detector sends a signal through th e charge pump and loop filter ( 8 ). the charge pump generates an error voltage to bring the vco back into alignment and the loop filter removes any high frequency noise before the error voltage en ters the vco. this new vco signal enters the clock tree to drive the chip's circuitry. f out represents the clock signal that emerges from the output pad (the output signal pllpad_out is explained in 4 8 ). this clock signal is mean ingful only when the pll is configured for external use; otherwise, it remains in high z state, as shown in the post-simulation waveform. vco filter fin fout + - 1st quadrant 2nd quadrant 3rd quadrant 4th quadrant clock tree frequency divide frequency multiply 1 . _ . 2 . _ . 4 . _ . 4 . _ . 2 . _ . 1 . . _ pll bypass
preliminary 8 most quicklogic products c ontain four plls, one to be used in each quadrant. the pll presented in 8 controls the clock tree in the fourth quadrant of its fpga. as previously mentioned, quicklogic plls compen sate for the additional delay created by the clock tree itself by subtracting the clock tree de lay through the feedback path. for more specific informatio n on the phase locked loops, please refer to quicklogic application note 58.
*!' " quicklogic plls have eight modes of operation, based on the input frequency and desired output frequency? 4 . indicates the features of each mode.
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preliminary 9 "
4 8 summarizes the key signals in quicklogic?s plls.
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input clock signal pll_reset active high reset if pll_reset is asserted, then clknet_out and pllpad_out are reset to 0. this signal must be asserted and then released in order for the lock_detect to work. onn_offchip pll output this signal selects whether the pll will drive the internal clock network or be used off-chip. this is a static signal, not a dynamic signal. tied to gnd = outgoing signal drives internal gates. tied to vcc = outgoing signal used off-chip. clknet_out out to internal gates this signal bypasses the pll logic before driving the internal gates. note that this signal cannot be used in the same quadrant where the pll signal is used (pllclk_out). pllclk_out out from pll to internal gates this signal can drive the internal gates after going through the pll. for this to work, onn_offchip must be tied to gnd. pllpad_out out to off-chip this outgoing signal is used off-chip. for this to work, onn_offchip signal must be tied to vcc. lock_detect active high lock detection signal note: for simulation purposes, this signal gets asserted after 10 clock cycles. however, it can take a maximum of 200 clock cycles to sync with the input clock upon release of the reset signal.
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): % 5 5 5 ! 5 ! ! ! 5 % 5 @ 5 % 5 @ 5 % 5 @ 5 @ 5 % lvttl n/a n/a -0.3 0.8 2.2 v ccio + 0.3 0.4 2.4 2.0 -2.0 lvcmos2 n/a n/a -0.3 0.7 1.7 v ccio + 0.3 0.7 1.7 2.0 -2.0 lvcmos18 n/a n/a -0.3 0.63 1.2 v ccio + 0.3 0.7 1.7 2.0 -2.0 gtl+ 0.88 1.12 -0.3 inref - 0.2 inref + 0.2 v ccio + 0.3 0.6 n/a 40 n/a pci n/a n/a -0.3 0.3 x v ccio 0.5 x v ccio v ccio + 0.5 0.1 x v ccio 0.9 x v ccio 1.5 -0.5 sstl2 1.15 1.35 -0.3 inref - 0.18 inref + 0.18 v ccio + 0.3 0.74 1.76 7.6 -7.6 sstl3 1.3 1.7 -0.3 inref - 0.2 inref + 0.2 v ccio + 0.3 1.10 1.90 8 -8
preliminary /1 $ 4
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thermal resistance equations: jc = ( t j - t c )/p ja = (tj - ta)/p p max = (t jmax - t amax ) / ja parameter description: jc : junction-to-case thermal resistance ja : junction-to-ambient thermal resistance t j : junction temperature t a : ambient temperature p: power dissipated by the device while operating p max : the maximum power di ssipation for the device t jmax : maximum junction temperature t amax : maximum ambient temperature note: 1
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, 8""$9&18" 0 ""$95" " voltage factor vs. supply voltage 0.9200 0.9400 0.9600 0.9800 1.0000 1.0200 1.0400 1.0600 1.0800 1.1000 2.25 2.3 2.35 2.4 2.45 2.5 2.55 2.6 2.65 2.7 2.75 supply voltage (v) kv temperature factor vs. operating temperature 0.85 0.90 0.95 1.00 1.05 1.10 1.15 -60 -40 -20 0 20 40 60 80 junction temperature c kt
preliminary // &
c!' " ?", the basic power equation which best mo dels power consumption is given below: p total = 0.350 + f [0.0031 lc + 0.0948 ckbf + 0.01 clbf + 0.0263 ckld + 0.543 ram + 0.20 pll + 0.0035 inp + 0.0257 outp ] (mw) where lc is the total number of logic cells in the design ckbf = # of clock buffers clbf = # of column clock buffers ckld = # of loads connected to the column clock buffers ram = # of ram blocks pll = # of plls inp is the number of input pins outp is the number of output pins note:
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7:-; " the following requirements must be met when powering up a device (refer to /1 ): when ramping up the power supplies keep (v ccio -v cc ) max 500 mv. deviation from this recommendation can cause perman ent damage to the device. v ccio must lead v cc when ramping the device. the power supply must be greater th an or equal to 400 s to reach v cc . ramping to v cc /v ccio before reaching 400 s can cause the device to behave improperly. voltage v ccio v cc (v ccio -v cc ) max 400 us v cc
preliminary /7 e" 4
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preliminary /0 the 1149.1 standard requires the following three tests: extest instruction. the extest instruction performs a pcb interconnect test. this test places a device into an external boundary test mode, selecting the boun dary scan register to be connected between the tap's test data in (tdi) and test data out (tdo) pins. boundary scan cells are preloaded with test patterns (v ia the sample/preload instruction), and input boundary cells capture the input data for analysis. sample/preload instruction. this instruction allows a device to remain in its functional mode, while selecting the boundary scan regist er to be connected between the tdi and tdo pins. for this test, the boundary scan register can be accessed via a data scan operation, allowing users to sample the functional data entering and leaving the device. bypass instruction. the bypass instruction allows data to skip a device's boundary scan entirely, so the data pa sses through the bypass register. th e bypass instruction allows users to test a device without passing through othe r devices. the bypass register is connected between the tdi and tdo pins, allowing serial data to be transferred through a device without affecting the operation of the device.
preliminary /. "
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' " tdi/rsi test data in for jtag/ram init. serial data in hold high during normal operation. connects to serial prom data in for ram initialization. connect to v cc if unused trstb/rro active low reset for jtag/ram init. reset out hold low during normal operation. connects to serial prom reset for ram initialization. connect to gnd if unused tms test mode select for jtag hold high during normal operation. connect to v cc if not used for jtag tck test clock for jtag hold high or low during normal operation. connect to v cc or ground if not used for jtag tdo/rco test data out for jtag/ram init. clock out connect to serial prom clock for ram initialization. must be left unconnected if not used for jtag or ram initialization io bank a io bank b v ccio (a) inref(a) ioctrl(a) io(a) v ccio (a) inref(a) ioctrl(a) io(a) io bank c io bank d v ccio (c) inref(c) ioctrl(c) io(c) v ccio (d) inref(d) ioctrl(d) io(d) io bank f io bank e v ccio (f) inref(f) ioctrl(f) io(f) v ccio (e) inref(e) ioctrl(e) io(e) io bank h io bank g (h) inref(h) ioctrl(h) io(h) v ccio v ccio (g) inref(g) ioctrl(g) io(g)
preliminary /8
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' " gclk global clock network driver low skew global clock. this pin provides access to a dedicated, distributed network capable of driving the clock, set, reset, f1, and a2 inputs to the logic cell, read, and write clocks, read and write enables of the embedded ram blocks, clock of the ecus, and output enables of the i/os. i/o(a) input/output pin the i/o pin is a bi-directional pin, configurable to either an input- only, output-only, or bi-directional pin. the a inside the parenthesis means that the i/o is located in bank a. if an i/o is not used, spde (quick works tool) provides the option of tying that pin to gnd, v cc, or tristate during programming. v cc power supply pin connect to 2.5 v supply v ccio (a) input voltage tolerance pin this pin provides the flexibility to interface the device with either a 3.3 v, 2.5 v, or 1.8 v device. the a inside the parenthesis means that v ccio is located in bank a. every i/o pin in bank a will be tolerant of v ccio input signals and will output v ccio level signals. this pin must be connected to either 3.3 v, 2.5 v, or 1.8 v. gnd ground pin connect to ground pllin pll clock input clock input for pll dedclk dedicated clock pin low skew global clock. this pin provides access to a dedicated, distributed clock network capable of driving the clock inputs of all sequential elements of the device (e.g. ram, flip flops). gndpll ground pin for pll connect to gnd inref(a) differential reference voltage the inref is the reference voltage pin for gtl+, sstl2, and sttl3 standards. follow the recommendations provided in 4 9 for the appropriate standard. the a inside the parenthesis means that inref is located in bank a. this pin should be tied to gnd if not needed. pllout pll output pin dedicated pll output pin. otherwise may be left unconnected ioctrl(a) highdrive input this pin provides fast reset, set, clock, and enable access to the i/o cell flip-flops, providing fast clock-to-out and fast i/o response times. this pin can also double as a high-drive pin to the internal logic cells. the a inside the parenthesis means that ioctrl is located in bank a. there is an internal pulldown resistor to ground on this pin. this pin should be tied to ground if it is not used. for backwards compatibility with eclipse, it can be tied to vcc or ground. if tied to vcc, it will draw no more than 20 a per ioctrl pin due to the pulldown resistor. <
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preliminary /9 vpump charge pump disable this pin disables the internal charge pump for lower static power operation. to disable the charge pump, connect vpump to 3.3 v. if the disable charge pump feature is not used, connect vpump to ground. for backwards compatibility with eclipse and eclipseplus devices, connect vpump to ground. vded voltage tolerance for clocks, jtag, and ioctrl/voltage drive for pllout and jtag pins this pin specifies the input voltage tolerance for clk, jtag, and ioctrl dedicated input pins, as well as the output voltage drive for pllout and jtag pins. if the plls are used, vded must be the same as v cc pll. for backwards compatibility with eclipse and eclipseplus devices, connect vded to 2.5 v. vccpll power supply pin for pll connect to 2.5 v supply or 3.3 v supply. for backwards compatibility with eclipse and eclipseplus devices, connect to 2.5 v.
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all unused, general purpose i/o pins can be tied to v cc , gnd, or hiz (high impedance) internally using the configuration editor. th is option is given in the botto m-right corner of the placement window. to use the placement editor, choose constraint > fix placement in the option pull- down menu of spde. the rest of the pins should be terminated at the board level in the manner presented in 4 // . /19-"
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) unused pll output pins must be connected to either v cc or gnd so that their associated input buffer never floats. utilized pll output pins that route the pll clock outside of the chip should not be tied to either v cc or gnd. ioctrl b ) )
alphabetical character. any unused pins of this type must be connected to either v cc or gnd. clk/pllin any unused clock pins should be connected to v cc or gnd. pllrst if a pll module is not used, then the associated pllrst must be connected to v cc ; under normal operation, use it as needed. inref if an i/o bank does not require the use of inref signal the pin should be connected to gnd. eclipse-e ql6250-e-6pq208c
preliminary 61 /19-" 4
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- " " - " " - " " - " " - " " %/2 ! 76 69( 90 69 /8 '3&%6g! .: 69 /" / < % ! 77 < 69 ( 9. < /9 '5 81 6g/ @" 6 "g 70 69( 98 69 /: < 8 69 /" 7 "g 7. < 99 69 61 '7 8/ 69" 0 690 78 69( 9: < 6 < 86 69" . 690 79 69( :1 69 6/ '8 87 69< 8 690 7: "g : 69 66 12 80 < 9 < 69 0 01 9 :/ 69 / 67 69@ 8. 69" : 690 0 %9b :6 6g/ @ 60 69@ 88 < 69 " 1 690 0/ "g % :7 69 / 6. 69@ 89 "g 69 /0 06 "g :0 69 68 "g 8: 69" / < 07 < % :. 69 69 < 69 @ 91 69" 6 6g/ @0 00 %/2 :8 69 6: 69@ 9 69" 7 69 /0 0. < :9 < 69 71 69@ 9/ < 0 690 08 69 :: 69 7 69@ 96 ' . 690 09 "g 11 69 7/ 69@ 97 < 8 690 0: 69 1 < 76 69@ 90 69c 9 690 .1 < 69 1/ %9b > 77 69 /@ 9. 69c : < 69 0 . 69 16 "g 70 6g/ @@ 98 69c /1 690 ./ 69 17 "g % 7. < 99 "g / "g .6 69 10 %/2 78 69 /@ 9: < 69 c // 690 .7 69 1. < % 79 69@ :1 69c /6 6 .0 69 18 69 7: 69@ : 69c /7 '> .. 69 19 "g 01 < 69 @ :/ 69 /c /0 ' .8 69 / 1: 69 0 69@ :6 69c /. < .9 6g/ @ 1 69 0/ 69@ :7 6g/ @c /8 '&%6g .: 69 / < 69 06 "g :0 < /9 '!&%6g 81 69 / 69 07 69@ :. 69 /c /: < 8 69 6 < 00 %9b ! :8 69c 61 '.& '&%6g> 8/ < 69 7 69 0. "g %> :9 69c 6 69( 86 69 0 69 08 "g :: 69c 6/ 69( 87 69 . 69 09 < % > /11 69c 66 "g 80 "g 8 69 / 0: %/2 > /1 69c 67 < 69 ( 8. < 9 6g/ @ .1 "g /1/ 69c 60 69( 88 69 : 69 / . 69" /16 < 69 c 6. 69( 89 /2 ( /1 69 ./ < 69 " /17 "g 68 69( 8: < / 69 .6 69" /10 69c 69 69( 91 69 // < 69 .7 69" /1. %9b 6: 69 /( 9 69 /6 "g .0 < /18 "g 71 6g/ @( 9/ 69 /7 69 .. 69" /19 "g %! 7 69 /( 96 "g /0 69 .8 69" 7/ 69( 97 < 69 /. 69 .9 69"
preliminary 6 /91f) " 4' f eclipse-e ql6250-e-6pt280c pin a1 corner
preliminary 6/ /91f) " 4
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f) " " f) " " f) " " f) " " f) " " f) " " %9b n!o #1 'n3oa% 6gn!o : 69 /n o d. 6a9no 7 6a9nco (6 6a9n(o / "g %n>o # < 69 n o 6g/ @n"o d8 6a9n o 0 "g (7 69 /n(o 6 6a9n@o #/ 6a9n o / 69 /n"o d9 6a9no . "g (0 < 69 n(o 7 6a9n@o #6 6a9n o 6 6a9n"o d: /2 ( 8 < (. 6a9n(o 0 6a9n@o #7 6a9n o 7 6a9n"o 6a9nco 9 < (8 9 . 69 /n@o #0 < 69 n o 0 "g / 6a9nco : "g (9 %/2 no 8 6a9n@o #. 6a9n o 0 < 6 < 69 nco 1 "g (: 6a9n(o 9 6a9n@o #8 6a9n o . 69 /n o 7 6a9nco < 5 %9b no : 6a9n@o #9 6a9n o 8 6a9n o 0 < / < 5/ "g %n!o 1 'n7o #: 6a9n o 9 6a9n o 0 "g 6 < 56 "g 6a9n o 6a9n"o : 6a9n o . 6a9no 7 < 57 6a9n0o / 6a9n o / 6a9n"o ) 6a9n"o 8 < 69 no 0 "g 50 6a9n0o 6 6a9n o 6 6a9n@o )/ 6a9n"o 9 6a9no . 6a9no 5. 69 /n0o 7 69 /n o 7 6a9n@o )6 69 /n"o : 6a9no 8 < 69 no 58 6a9n0o 0 6a9n o 0 6a9n@o )7 6a9n"o 6a9nco 9 6a9no 59 6a9n0o . 6a9n o . 6a9n@o )0 < / 6a9nco : 6a9no 5: 6a9n0o 8 6a9n o 8 6a9n@o )0 < 6 6a9nco 4 6a9nco 51 'no 9 %/2 no 9 6a9n@o ). 6a9n o 7 6a9nco 4/ 6a9nco 5 'n.o 'a%6gn>o : "g : 'n8o )8 6a9n o 0 < 46 6a9n0o 5/ 6a9n(o f %/2 n>o 1 6a9n o )9 6a9n o 0 < 47 6a9n0o 56 6a9n(o f/ "g 6a9n o ): 6a9n o . 6g/ @no 40 6a9n0o 57 6g/ @n(o f6 6a9n@o / 6a9n o 6a9n"o 8 6a9no 4. 69 /n0o 50 6a9n(o f7 6a9n@o 6 6g/ @n o / 6a9n"o 9 6a9no 48 6a9n0o 5. 6a9n(o f0 6a9n@o 7 6a9n o 6 6a9n"o : 6a9no 49 6a9n0o 58 6a9n(o f. 6g/ @n@o 0 6a9n o 7 6a9n"o % 69 /nco 4: 6a9n0o 59 "g %no f8 6a9n@o . 6a9n o 0 < %/ 6a9nco 41 6a9n0o 5: "g f9 6a9n@o 8 6a9n o 0 < %6 6a9nco 4 'n!oa% 6gno > "g f: 12 9 6a9n o . < %7 6a9nco 4/ 6a9n(o >/ %/2 n!o f1 'n5o : 6a9n o 8 6a9n o %0 < 46 6a9n(o >6 6a9n0o f 6a9n o 6a9n"o 9 6a9n o %0 < 47 6a9n(o >7 6a9n0o f/ 6a9n o / 6a9n"o : 6a9n o %. 6a9no 40 6a9n(o >0 6a9n0o f6 69 /n o 6 < 69 n"o e 6a9n"o %8 6a9no 4. 6a9n(o >. 6a9n0o f7 6a9n o 7 6a9n@o e/ 6a9n"o %9 69 /no 48 < % no >8 6a9n0o f0 6a9n o 0 "g e6 < 69 n"o %: 69 /no 49 6a9n(o >9 6a9n0o f. 6a9n o . < e7 6a9n"o 6a9nco 4: 6a9n(o >: 6 f8 < % no 8 < e0 "g / 6a9nco ( 6a9n0o >1 'noa%6gno f9 "g %no 9 < e0 < 6 69 /nco (/ 6a9n0o > 6a9n(o f: %9b n>o : < e. 6a9no 7 6g/ @nco (6 < % n!o >/ 6a9n(o # 6a9n@o 1 "g e8 < 69 n o 0 < (7 6a9n0o >6 6a9n(o #/ < % n>o "g e9 6a9n o 0 "g (0 < 69 n0o >7 69 /n(o #6 6a9n@o / < e: 6a9n o . 6a9no (. 6g/ @n0o >0 6a9n(o #7 6a9n@o 6 < d < 8 6a9no (8 6a9n0o >. 6a9n(o #0 < 69 n@o 7 "g d/ ' 9 6a9no (9 6a9n0o >8 6a9n(o #. 69 /n@o 0 < d6 6a9n"o : 6a9no (: < 69 n0o >9 6a9n(o #8 6a9n@o . 6a9n o d7 6a9n"o 6a9nco (1 'n>o >: %9b no #9 6a9n@o 8 < 69 n o d0 "g / 6a9nco ( < 69 n(o #: < 69 n@o 9 6g/ @n o d0 "g 6 < 69 nco (/ 6a9n(o
preliminary 66 797f) " 4' f eclipse-e ql6250-e-6ps484c 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c e d f g h k j l m n r p t u v y w 22 21 ab aa pin a1 corner pin a1
preliminary 67 797f) " 4
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f) " " f) " " f) " " f) " " f) " " f) " " g # g 69 /n0o ) g e 6a9n0o 'n.o 'a%6gn>o / %/2 n!o #/ 6a9n0o / 6a9n0o )/ g e/ 6a9n0o / 'n>o 6 6a9n0o #6 < % n!o 6 6a9n0o )6 6a9n0o e6 6a9n0o 6 'noa%6gno 7 6a9n0o #7 %9b no 7 6a9n0o )7 6a9n0o e7 6a9n0o 7 6a9n0o 0 6a9n0o #0 6a9n0o 0 g )0 6a9n0o e0 6a9n0o 0 6a9n0o . g #. g . 6a9nco ). 6a9n0o e. 6a9n0o . 6a9n0o 8 6a9nco #8 6a9nco 8 g )8 "g e8 6a9n0o 8 "g 9 69 /nco #9 g 9 6a9nco )9 6a9nco e9 < 9 "g : 6a9nco #: 69 /nco : 6a9nco ): 6a9nco e: "g : "g 1 g #1 g 1 6a9nco )1 g e1 < 1 "g g # 6a9nco < ) 6a9n"o e < "g / ' #/ g / 6a9n"o )/ "g e/ "g / "g 6 6a9n"o #6 6a9n"o 6 6a9n"o )6 g e6 < 6 "g 7 6a9n"o #7 g 7 g )7 g e7 "g 7 < 0 6a9n"o #0 6a9n"o 0 69 /n"o )0 6a9n"o e0 < 0 < . g #. 6a9n"o . 6a9n"o ). < e. 6a9n@o . 'n5o 8 6a9n"o #8 g 8 6g/ @n"o )8 < 69 n@o e8 < 69 n@o 8 < 69 n@o 9 6a9n"o #9 6a9n"o 9 g )9 6a9n@o e9 6a9n@o 9 6a9n@o : 6a9n@o #: 6a9n@o : 6a9n@o ): 6a9n@o e: 6a9n@o : 'n8o /1 "g #/1 "g %n>o /1 6a9n@o )/1 6a9n@o e/1 6a9n@o /1 6a9n@o / %9b n!o #/ 6a9n@o / g )/ 6g/ @n@o e/ 6a9n@o / g // 6a9n@o #// 6a9n@o // 6a9n@o )// 6a9n@o e// 6a9n@o // 6a9n@o f 6a9n0o 6a9n0o 6a9n0o 6a9n0o d 6 6a9n(o f/ "g / 6a9n0o / 6g/ @n0o / 6a9n0o d/ 6a9n0o / 6a9n(o f6 "g %n!o 6 6a9n0o 6 g 6 6a9n0o d6 6a9n0o 6 6a9n(o f7 "g 7 6a9n0o 7 6a9n0o 7 6a9n0o d7 6a9n0o 7 'n!oa%6gno f0 6a9n0o 0 6a9n0o 0 6a9n0o 0 69 /n0o d0 6a9n0o 0 g f. 6a9nco . 6a9nco . < 69 n0o . < 69 n0o d. < 69 n0o . < 69 n(o f8 6a9nco 8 g 8 < 69 nco 8 6a9nco d8 g 8 'no f9 6g/ @nco 9 6a9nco 9 6a9nco 9 "g d9 < 9 < f: 6a9nco : g : < 69 nco : < d: < : < f1 6a9nco 1 6a9nco 1 6a9nco 1 < d1 "g 1 "g f 6a9nco 6a9nco < 69 nco < d "g "g f/ g / 6a9n"o / < 69 n"o / "g d/ "g / "g f6 g 6 6a9n"o 6 6a9n"o 6 < d6 "g 6 "g f7 g 7 6a9n"o 7 < 69 n"o 7 < d7 < 7 "g f0 g 0 69 /n"o 0 g 0 "g d0 < 0 "g f. 6a9n"o . 6a9n"o . < 69 n"o . 6a9n@o d. g . "g f8 6a9n"o 8 6a9n"o 8 g 8 6a9n@o d8 6a9n@o 8 6a9n o f9 6a9n"o 9 6a9n@o 9 6a9n@o 9 g d9 6a9n@o 9 6a9n o f: %/2 n>o : < % n>o : 6a9n@o : 6a9n@o d: g : 6a9n o f/1 6a9n@o /1 6a9n@o /1 69 /n@o /1 6a9n@o d/1 6a9n@o /1 'n7o f/ 6a9n@o / 6a9n@o / 6a9n@o / 6a9n@o d/ 6a9n@o / 'n3oa%6gn!o f// 6a9n@o // 6a9n@o // 69 /n@o // g d// g // 12 <
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preliminary 60 % g . 6a9n o 4: g 5/ 6a9n(o >8 g 1 6a9no %/ 6a9n(o 8 g 41 /2 ( 56 6a9n(o >9 6a9n o 6a9no %6 6a9n(o 9 6a9n o 4 "g 57 6a9n(o >: g / 6a9n o %7 g : g 4/ g 50 6a9n(o >/1 6a9n o 6 6a9n o %0 6a9n(o /1 6a9n o 46 6a9n o 5. g >/ g 7 6a9n o %. g / 6a9n o 47 g 58 6a9no >// 6a9n o 0 6a9n o %8 g // 6a9n o 40 6a9n o 59 6a9no g 6a9n(o . g %9 < 6a9n(o 4. "g 5: g g/ 6a9n(o 8 g %: < / 6g/ @n(o 48 6a9n o 51 6a9no g6 < % no 9 6a9n o %1 "g 6 6a9n(o 49 6a9n o 5 g g7 6a9no : 6a9n o % "g 7 6a9n(o 4: g 5/ < g0 6a9no /1 "g %no %/ "g 0 6a9n(o 4/1 g 56 g g. 6a9no / 6a9n o %6 "g . g 4/ 69 /n o 57 6a9n o g8 6a9no // 6a9n o %7 < 8 6a9n(o 4// 6a9n o 50 6a9n o g9 69 /no f 6a9n(o %0 < 9 "g ( 69 /n(o 5. 6g/ @n o g: 6a9no f/ "g %no %. 6a9n o : < (/ 6a9n(o 58 6a9n o g1 6a9no f6 %/2 no %8 < 69 n o 1 < (6 69 /n(o 59 6a9n o g 6a9n o f7 6a9n(o %9 6a9n o "g (7 6a9n(o 5: 6a9n o g/ g f0 6a9n(o %: 6a9n o / < (0 6a9n(o 5/1 6a9n o g6 g f. 6a9no %/1 6a9n o 6 < (. 6a9no 5/ 6a9n o g7 6a9n o f8 6a9no %/ 6a9n o 7 < (8 < 69 no 5// 6a9n o g0 69 /n o f9 69 /no %// 6a9n o 0 "g (9 g > 6a9n(o g. 6a9n o f: 6a9no g . 6a9n o (: < 69 no >/ 6a9n(o g8 6a9n o f1 6a9no / 6a9n(o 8 < 69 n o (1 6a9no >6 6a9n(o g9 6a9n o f g 6 6a9n(o 9 6a9n o ( < 69 no >7 6a9n(o g: %9b n>o f/ 6a9n o 7 6a9n(o : 6a9n o (/ < 69 n o >0 6a9n(o g/1 %/2 no f6 6a9n o 0 6a9n(o /1 6a9n o (6 6a9n o >. 6a9no g/ 6a9n o f7 g . < 69 n(o / 6a9n o (7 < 69 n o >8 g g// 6a9n o f0 6a9n o 8 6a9n(o // 6a9n o (0 g >9 g 9 f. 69 /n o 9 < 4 6a9n(o (. < 69 n o >: g / %9b no f8 6a9n o : "g 4/ 6a9n(o (8 < 69 n o >1 g 6 "g f9 6a9n o 1 < 46 6a9n(o (9 6a9n o > 6a9no 7 6a9n(o f: 6a9n o "g 47 6a9n(o (: 6a9n o >/ g 0 6a9no f/1 "g / < 40 6a9n(o (/1 69 /n o >6 6a9n o . 6a9no f/ < % no 6 < 4. < 69 n(o (/ g >7 g 8 g f// 6a9n o 7 "g 48 "g (// 6g/ @n o >0 6a9n o 9 6g/ @no 0 < 49 6a9no 5 6a9n(o >. g : g
3.8.%("0%
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5' 3 %" #" "* " telephone: 408 990 4000 (us) 416 497 8884 (canada) 44 1932 57 9011 (europe) 49 89 930 86 170 (germany) 852 8106 9091 (asia) 81 45 470 5525 (japan) e-mail: info@quicklogic.com support: support@quicklogic.com web site: http://www.quicklogic.com/
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,
5/+ c )
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a december 2002 brian faith, andreea rotaru ql 6250-e - 6 pq208 c quicklogic device eclipse-e device part number speed grade 6 = faster 7 = fastest operating range c = commercial i = industrial m = military package code pq208 = 208-pin pqfp pt280 = 280-pin fpbga (0.8 mm) ps484 = 484-pin bga (1.0 mm)
preliminary 68 #',
"4 $ "* " copyright ? 2002 quicklogic corporation. all rights reserved. the information contained in this document and the accomp anying software programs is protected by copyright. all righ ts are reserved by quicklog ic corporation. quicklogic corporation reserves the right to modify this document without any obligation to notify any person or entity of such revision. copying, duplica ting, selling, or otherwis e distributing any part of this product without the prior written consent of an authorized representative of quicklogic is prohibited. quicklogic and the quicklogic logo, pasic, vialink, deskfab, and quickworks are registered trademarks of quicklogic corporation; ecli pse, quickfc, quickdsp, quickdr, quicksd, quicktools, quickcore, quickpro, spde, webasic, and webesp are trademarks of quicklogic corporation.
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